As I have mentioned in previous posts, it is important for all of the basic building blocks to have similar sizes and delays, so that they are compatible in larger circuits.  The next level of abstraction is that of tiles, which each tile representing a single wire or gate.  By holding ourselves to strict requirements for the underlying gates, we will be able to run our simulations in terms of tiles, without needing to simulate the underlying metapixels.  I’ve said a few things about bounding boxes and delays, but now is time to get a lot more specific.

The Standard

We have settled on 11×11 metapixel components.  The figure below show the typical layout of a single gate.  The top and left sides are input, and the right side is output.  The red box is 11×11 (inclusive), and the red itself denotes cells that cannot be occupied by the gate.  This is to provide the necessary 1-cell-wide padding to prevent interference between components.  The output side is the only side that doesn’t need buffering, since buffering is provided by the input side of the adjacent component.   The blue and green cells denote the mandatory wire buffers.

typical unit bounding box

Every logic gate in the previous post can fit into a bounding box like this, and so can many of the wire components (the others won’t be used individually).

As far as timing is concerned, the distance between signals will be a multiple of 11 (often 22 for data), so a gate should be able to receive electrons every 11 ticks, and give the output exactly 11 ticks later.  The only exceptions are the 22:11 and 33:11 delay wire units, which of course delay their output to a different multiple of 11.

When testing a new gate, it is important to include a length of wire on every side so that you can actually see if any erroneous/malformed electrons are produced.

Time-Keeping Components

The two main types of timing components (clocks and delay wires) must be special-built for 11-cell-based technology.  Delay wires will be used to increase the delay between two components without having to increase the travel distance between them.  Especially important is a 22:11 delay, which solves the checkerboard parity problem (moving an odd Manhattan distance in an even number of ticks).  Clocks are used to synchronize the circuits and to create inverted gates.  Ultimately, a couple large clocks will likely control the computer.  Here are some delay wire units ( which were also previously featured on the “Building Blocks: Wires” post) and some small clocks:

22:11 delay wire
33:11 delay wire
11-tick clock
22-tick clock
33-tick clock

Multi-tile Components

Sometimes, components don’t fit into a single tile, but rather occupies the space of a group of tiles.  There are typically two causes of this:

  1. An 11×11 square is sometimes simply not enough space, and it’s not something that can be made with two separate tiles next to each other.  We did consider larger tile sizes for our standard, like 16×16, but changing 11×11 to 16×16 would double the total area of the rest of the computer and dramatically increase the amount of empty space.
  2. The given component can be made using existing components, but can be made significantly smaller by compacting its sub-components together.  An example of this is the serial binary adder, which will be the subject of a future post.

In these cases, the component can be considered a “multi-tile” component, which fits neatly into a 11-wide grid but which can’t be divided into independent 11×11 squares.  The multi-tile component will be treated as a single unit during simulation, without needing to simulate the different sub-components.  Below is an example of a 33-clock in the form of a 2×1 multi-tile.

33-clock, a multi-tile component. It is actually period-66 (too long for the GIF creator), and can be converted to a 66-clock.

The timing of multi-tile components is more complicated, since their delays are influenced by their size and complexity.  They should be able to receive input and give output every N*11 generations, for some integer N.  The delay between input and output should be a multiple of 11 as well.  A multi-tile component is considered “lagless” if the delay between input and output equals the distance between them.  A component is “linear” if the input is aligned (either horizontally or vertically) with the output, so that the signal travels in a straight line.

Tile-Based Circuit Simulator

Conor is currently working on a tile-based circuit simulator, which will served as the next (and possibly final) platform for circuit design.  His software will be able to simulate tile and multi-tile components without needing to worry about the underlying metapixel structure, allowing for easier development of complex circuits.

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